1. Field of the Invention
The present invention relates to means for dynamically altering the threshold voltage of Silicon-On-Insulator (SOI) transistors, and more particularly to the application of SOI transistor unit cells in large scale integrated logic circuits to provide high performance, low power integrated circuits incorporating SOI transistor devices with adjustable threshold voltages.
2. Background Art
It is known that threshold voltages of SOI devices can be altered by changing the body-source bias potential. References that relate generally to adjusting the bias voltage of CMOS devices or to SOI devices and their application are as follows.
U.S. Pat. No. 5,610,533 issued to Arimoto et al. discloses a semiconductor circuit that converts body bias potential between first and second values for MOS-FET logic circuits.
U.S. Pat. No. 5,608,344 issued to Marlow discloses an analog double-throw switch that connects the body of a FET to either a first voltage or a second voltage.
U.S. Pat. No. 5,557,231 issued to Yamaguchi et al. discloses a semiconductor device in combination with a first bias voltage generating circuit for generating a first substrate bias voltage value for reducing power consumption in the standby state and a second bias voltage generating circuit for generating a second substrate bias voltage value for increasing operating speed in the active state.
U.S. Pat. No. 5,552,723 to Shigehara et al. discloses a body bias switch for MOSFET devices with two N channel FETs, one with a common gate with the FET being controlled, the other FET with a gate controlled by the complement of the signal at the gate of the FET being controlled.
U.S. Pat. No. 5,461.338 issued to Hirayama et al. discloses a circuit with a plurality of transistors on a substrate and a bias voltage generating circuit for providing a low threshold bias voltage in the active state for high speed operation and a high threshold bias voltage for power consumption the standby state.
U.S. Pat. No. 4,809,056 to Shirato et al. discloses a technique for fabricating an improved contact region of a SOI structure.
U.S. Pat. No. 5,185,535 to Farb et el. discloses separately controllable and independent back bias for adjacent CMOS transistors fabricated on SOI substrates.
Other background references include U.S. Pat. No. 5,594,371 to Douseki, U.S. Pat. No. 5,602,790 to Mullarkey, U.S. Pat. No. 5,546,020 to Lee et al., U.S. Pat. No. 5,317,181 to Tyson, U.S. Pat. No. 5,422,583 to Blake et al., U.S. Pat. No. 4,612,461 to Sood, U.S. Pat. No. 4,791,316 to Winnerl et al., U.S. Pat. No. 5.045,716 to Takacs et al., U.S. Pat. No. 5,103,277 to Caviglia et al., and U.S. Pat. No. 5,341,034 to Matthews.